Effects of package parasitics on substrate and interconnection crosstalk in mixed-signal CMOS ICs

This paper presents an experimental evaluation of crosstalk effects due to current pulses drawn from voltage supplies in mixed analog-digital CMOS integrated circuits. A test chip was designed in 0.18-$\mu$m CMOS technology, integrated and mounted in two different ways, namely, in JLCC package and with flip-chip assembly technique, in order to compare measurement results. As expected, the circuit assembled with the flip-chip technique has better immunity to disturbances generated by the digital section, due to the lower values of interconnection parasitics.