A very compact population count circuit for associative memories

This paper presents a new population count circuit, suitable for very scaled CMOS technologies. The proposed circuit is optimized for the total area, instead of the number of transistors, in order to take full advantage of deeply scaled technology features. Moreover, the circuit is purely combinational, in order to simplify the control logic. The envisaged solution has been designed in a commercial 28 nm CMOS technology, and the design of the layout has been validated. The total silicon area is 14.04 x 0.905 mu m(2) for a counter from 0 to 8.