A threshold voltage modeling for a spacer-trapping memory cell using Verilog-A

The threshold voltage of the flash memories varies with respect to the applied voltages at the respective terminal of a memory cell. This paper presents the modeling of the threshold voltage variation for an embedded spacer-trapping memory cell. The effects such as velocity saturation of the transistor and the band-to-band tunneling mechanism have been incorporated in the model. The proposed memory model has been simulated in a standard 0.18 μm CMOS technology. The output results of the proposed model using Verilog-A shows 94.9 ms of erasing time for the programing time of 33.4 ms and for a memory speed of 10 kHz. An increment of 930 mV of the threshold voltage during the programming mode has been recorded.