Layout-oriented simulation of on-destructive single event effects in CMOS IC blocks

This paper presents a tool based on a two dimensional charge-collection simulation to study non-destructive single event effects in CMOS IC blocks. The interaction between the radiation particle and the p-n junctions is modeled at circuit level with a set of parasitic currents, which are injected into the nodes corresponding to the geometrical areas at or near the point where the particle hits the IC. A drift-diffusion model is used to obtain parasitic currents waveforms. By means of circuit simulations, single event transients and single event upsets can be obtained for different collision positions. From simulation results, a map can be drawn, showing the sensitivity to single events of different layout regions. By comparing sensitivity maps, the designer can choose the most robust layout with respect to single event effects. Layout design guidelines are proposed to improve radiation hardness.