Models and parameters for crosstalk simulation

This chapter illustrates a simplified model for analysis of crosstalk effects in deep submicron CMOS technologies. Most parameters for parasitic element values can be easily obtained by technology information contained in the physical design rules. However, the substrate bias resistance, which is one of the most important parasitic elements in CMOS technologies with highly-doped substrate with epitaxial layer, is usually neglected in the silicon foundry documentation. The substrate bias resistance value can be obtained either from technology parameters or by experimental measurements on a test structure, and crosstalk effects can be easily estimated through a SPICE-level simulation. The proposed approach has been validated by comparing results with simulations after extracting parasitics with a commercial tool and with experimental measurements on a test chip.