A radiation hardened 512 kbit SRAM in 180 nm CMOS technology

A 512 kbit static random access memory has been designed and fabricated in a single-poly, six-metal 180 nm CMOS technology, with 1.8 V supply. The circuit has been designed to be radiation hard. The basic memory cell is a six transistor cell with a Miller capacitor between the internal latch nodes, to mitigate single event upset. Architectural and circuital solutions are also proposed to mitigate transient propagation and functional interrupts due to single events. Edge-less transistors were used to avoid damaging effects due to total dose. Guard rings and a large numbers of substrate and n-well contacts were placed to mitigate single event latch-up. A layout-oriented simulation technique has been used to estimate the cell sensitivity to single event effects. Measurements on silicon prototypes demonstrate that the memory is functional, with a write delay time equal to 13.7 ns and a read delay time equal to 18.5 ns. Post-irradiation measurements confirm that the 512 kbit SRAM is rad-hard up to 2 Mrad of total ionizing dose (TID).