A threshold voltage modeling for a spacer-trapping memory cell using Verilog-A
Contributo in Atti di convegno
Data di Pubblicazione:
2014
Citazione:
A threshold voltage modeling for a spacer-trapping memory cell using Verilog-A / H. Shrimali, V. Liberali - In: Synthetic LNA/DNA nano-scaffolds for highly efficient diagnostics of nucleic acids and autoimmune antibodies / [a cura di] I.K. Astakhova. - [s.l] : CRC, 2014. - ISBN 9781482258271. - pp. 529-532 (( convegno MEMS, Fluidics, Bio Systems, Medical, Computational and Photonics tenutosi a Washington nel 2014.
Abstract:
The threshold voltage of the flash memories varies with respect to the applied voltages at the respective terminal of a memory cell. This paper presents the modeling of the threshold voltage variation for an embedded spacer-trapping memory cell. The effects such as velocity saturation of the transistor and the band-to-band tunneling mechanism have been incorporated in the model. The proposed memory model has been simulated in a standard 0.18 μm CMOS technology. The output results of the proposed model using Verilog-A shows 94.9 ms of erasing time for the programing time of 33.4 ms and for a memory speed of 10 kHz. An increment of 930 mV of the threshold voltage during the programming mode has been recorded.
Tipologia IRIS:
03 - Contributo in volume
Keywords:
EEPROM memory characteristics simulation; MOS capacitance characteristics; Non-volatile memory; Tunneling; Hardware and Architecture; Electrical and Electronic Engineering; Electronic, Optical and Magnetic Materials
Elenco autori:
H. Shrimali, V. Liberali
Link alla scheda completa:
Titolo del libro:
Synthetic LNA/DNA nano-scaffolds for highly efficient diagnostics of nucleic acids and autoimmune antibodies