Fault-tolerant high-performance CORDIC processors

This paper presents a low-cost approach to concurrent error detection in a high-performance CORDIC processor based on a conditional-sum scheme. The specific characteristics of the CORDIC computation and the processor allow fault detection at a low increase in circuit complexity and latency. The detection scheme is based on use of the AN codes for the arithmetic part and on duplication of the rotation direction generators. Granular-pipelining has been applied to provide a variety of different performance tradeoffs, all with the same fault detection capabilities.