Data di Pubblicazione:
2004
Citazione:
A time-domain current model for fully CMOS logic gates / V. Ferragina, N. Ghittori, G. Torelli, G. Trucco, G. Boselli, V. Liberali - In: NEWCAS 2004 : the 2. Annual IEEE northeast workshop on circuits and systems : conference proceedings : 20-23 june, 2004, Montreal, Canada / [a cura di] [s.n.]. - Piscataway : Institute of electrical and electronics engineers, 2004. - ISBN 0780383222. - pp. 29-32 (( Intervento presentato al 2. convegno IEEE Northeast Workshop on Circuits and Systems tenutosi a Montréal nel 2004 [10.1109/NEWCAS.2004.1359007].
Abstract:
This paper presents two complementary approaches for simulation of mixed-signal CMOS integrated circuits, aiming at estimating crosstalk effects by identifying possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. The two simulation algorithms have different levels of detail, so that their computational speed and level of accuracy are different. A simple expression of voltage and current in the pull-up and the pull-down branches of a CMOS logic gate can be derived. Computer simulations demonstrate the feasibility of the proposed approaches.
Tipologia IRIS:
03 - Contributo in volume
Keywords:
CMOS logic circuits ; SPICE ; Circuit simulation ; Crosstalk ; Digital simulation ; Logic gates ; Mixed analogue-digital integrated circuits ; Time-domain analysis.
Elenco autori:
V. Ferragina, N. Ghittori, G. Torelli, G. Trucco, G. Boselli, V. Liberali
Link alla scheda completa:
Titolo del libro:
NEWCAS 2004 : the 2. Annual IEEE northeast workshop on circuits and systems : conference proceedings : 20-23 june, 2004, Montreal, Canada