Data di Pubblicazione:
2007
Citazione:
High-level architecture of an IPSec-dedicated system on chip / A. Ferrante, V. Piuri - In: 2007 next generation Internet networks : 3. EURO-NGI conference on next generation Internet networks : design and engineering for heterogeneity : NGI 2007 : 21 - 23 may 2007, Trondheim, Norway / [a cura di] [s.n.]. - Piscataway : Institute of electrical and electronics engineers, 2007. - ISBN 1424408563. - pp. 159-166 (( Intervento presentato al 3. convegno EuroNGI Conference on Next Generation Internet Networks (NGI) tenutosi a Trondheim, Norway nel 2007.
Abstract:
IPSec is a suite of protocols which adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. In this paper we propose a high level architecture of a system on chip (SoC) which implements IPSec. This SoC has been thought to be placed on the main data path of the host machine (flow-through architecture), thus allowing for transparent processing of IPSec traffic. The functionalities of the different blocks and their interactions, along with an estimation of the internal memory size, are also shown.
Tipologia IRIS:
03 - Contributo in volume
Keywords:
IP networks ; cryptographic protocols ; Logic design ; System-on-chip ; Telecommunication security ; Telecommunication traffic.
Elenco autori:
A. Ferrante, V. Piuri
Link alla scheda completa:
Titolo del libro:
2007 next generation Internet networks : 3. EURO-NGI conference on next generation Internet networks : design and engineering for heterogeneity : NGI 2007 : 21 - 23 may 2007, Trondheim, Norway