A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC
Articolo
Data di Pubblicazione:
2017
Citazione:
A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC / A. Paternò, L. Pacher, E. Monteil, F. Loddo, N. Demaria, L. Gaioni, F.D. Canio, G. Traversi, V. Re, L. Ratti, A. Rivetti, M.D.R. Rolo, G. Dellacasa, G. Mazza, C. Marzocca, F. Licciulli, F. Ciciriello, S. Marconi, P. Placidi, G. Magazzù, A. Stabile, S. Mattiazzo, C. Veri. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - 12:02(2017 Feb).
Abstract:
This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC. A 64 x 64 matrix of 50 x 50 mu m(2) pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm(2) pixel rate, trigger frequency of 1MHz and 12.5 mu sec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.
Tipologia IRIS:
01 - Articolo su periodico
Keywords:
Front-end electronics for detector readout; Particle tracking detectors (Solid-state detectors); Radiation-hard electronics
Elenco autori:
A. Paternò, L. Pacher, E. Monteil, F. Loddo, N. Demaria, L. Gaioni, F.D. Canio, G. Traversi, V. Re, L. Ratti, A. Rivetti, M.D.R. Rolo, G. Dellacasa, G. Mazza, C. Marzocca, F. Licciulli, F. Ciciriello, S. Marconi, P. Placidi, G. Magazzù, A. Stabile, S. Mattiazzo, C. Veri
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