A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms
Articolo
Data di Pubblicazione:
2000
Citazione:
A serial-parallel architecture for two-dimensional discrete cosine and inverse discrete cosine transforms / H. Lim, V. Piuri, E.E. Swartzlander Jr.. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - 49:12(2000), pp. 1297-1309.
Abstract:
The Discrete Cosine and Inverse Discrete Cosine Transforms are widely used tools in many digital signal and image processing applications. The complexity of these algorithms often requires dedicated hardware support to satisfy the performance requirements of hard real-time applications. This paper presents the architecture of an efficient implementation of a two-dimensional DCT/IDCT transform processor via a serial-parallel systolic array that does not require transposition.
Tipologia IRIS:
01 - Articolo su periodico
Keywords:
Application specific processor architecture; Discrete Cosine Transform; Image compression; Inverse Discrete Cosine Transform; Serial-parallel processor; Systolic array
Elenco autori:
H. Lim, V. Piuri, E.E. Swartzlander Jr.
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